
54
8018P–AVR–08/10
ATmega169P
10.5
Register Description
10.5.1
MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
10.5.2
WDTCR – Watchdog Timer Control Register
Bits 7:5 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
Bit
765
43210
0x35 (0x55)
–
JTRF
WDRF
BORF
EXTRF
PORF
MCUSR
Read/Write
R
R/W
Initial Value
0
See Bit Description
Bit
765
432
10
(0x60)
–
WDCE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R/W
Initial Value
0